The present invention relates generally to memory systems and in particular to systems and methods for accurately reading multi-bit flash memory devices.
Flash memory is a type of electronic memory media that can be rewritten and that can retain content without consumption of power. Flash memory devices generally have life spans from 100 K to 300 K write cycles. Unlike dynamic random access memory (DRAM) devices and static random memory (SRAM) devices in which a single byte can be erased, flash memory devices are typically erased and written in fixed multi-bit blocks or sectors. Flash memory technology evolved from electrically erasable read only memory (EEPROM) chip technology, which can be erased in situ. Flash memory devices are less expensive and more dense as compared to many other memory devices, meaning that flash memory devices can store more data per unit area. This new category of EEPROMs has emerged as an important non-volatile memory that combines advantages of erasable programmable read only memory (EPROM) density with EEPROM electrical erasability.
Conventional flash memory devices are constructed in a cell structure wherein a single bit of information is stored in each cell. In such single bit memory architectures, each cell typically includes a metal oxide semiconductor (MOS) transistor structure having a source, a drain, and a channel in a substrate or P-well, as well as having a stacked gate structure overlying a channel. The stacked gate may further include a thin gate dielectric layer (sometimes referred to as a layer of tunnel oxide) formed on the surface of a substrate or P-well. The stacked gate also includes a polysilicon floating gate overlying the tunnel oxide and an interpoly dielectric layer overlying the floating gate. The interpoly dielectric is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate overlies the interpoly dielectric layer.
The control gate is connected to a wordline associated with a row of such cells to form sectors of such cell in a typical NOR configuration. In addition, the drain regions of the cells are connected together by a conductive bitline. The channel of the cell formed between the source and drain regions conducts current between the source and drain in accordance with an electric field formed in the channel by a voltage applied to the stacked gate structure by a wordline attached to the stacked gate structure. In the NOR configuration, each drain terminal of the transistors within a column is connected to the same bitline. In addition, the stacked gate structure of each flash cell in a row is connected to the same wordline. Typically, the source terminal of each cell is connected to a common source terminal. In operation, individual flash cells are addressed via the respective bitline and wordline employing peripheral decoder and control circuitry for programming (writing), reading and erasing the cell.
The single bit stacked gate flash memory cell is programmed by applying a programming voltage to the control gate, connecting the source to ground and connecting the drain to a programming voltage. The resulting high electric field across the tunnel oxide results in a phenomenon deemed xe2x80x9cFowler-Nordheimxe2x80x9d tunneling. During Fowler-Nordheim tunneling, electrons in the channel region tunnel through the gate oxide into the floating gate and become trapped in the floating gate. As a result of the trapped electrons, the threshold voltage of the cell increases. This change in the threshold voltage VT (and thereby the channel conductance) of the cell created by the trapped electrons causes the cell to be programmed.
In order to erase a typical single bit stacked gate flash memory cell, a voltage is applied to the source, the control gate is held at a negative potential, and the drain is allowed to float. Under these conditions, an electric field is developed across the tunnel oxide between the floating gate and the source. The electrons that are trapped in the floating gate flow toward and cluster at a portion of the floating gate overlying the source region. The electrons are then extracted from the floating gate and into the source region by way of Fowler-Nordheim tunneling through the tunnel oxide. The cell is erased as the electrons are removed from the floating gate.
In conventional single bit flash memory devices, erase verification is performed to determine whether each cell in a block or set of cells has been properly erased. Current single bit erase verification methodologies provide for verification of bit or cell erasure, and application of supplemental erase pulses to individual cells that fail the initial verification. Thereafter, the erased status of the cell is again verified and the process continues until the cell or bit is successfully erased or the cell is marked as unusable.
Recently, multi-bit flash memory cells have been introduced that allow the storage of multiple bits of information in a single memory cell. Techniques that have been developed with conventional single bit flash memory devices do not work well for the new multiple bit flash memory cells. For example, a dual bit flash memory structure has been introduced that does not utilize a floating gate, such as an ONO flash memory device that employs a polysilicon layer over the ONO layer for providing wordline connections. In a dual bit memory device, one side of a dual bit memory cell is called a complimentary bit (CB) and the other side of the dual bit memory cell is called a normal bit (NB). The dual bit memory cell uses a layer of nitride in an ONO (oxide-nitride-oxide) stack to store charge; and since nitride is not a conductor, the charge added or removed during the program and erase operations should not redistribute to other regions of the layer of nitride. However, the buildup of charge and leakage in one bit does effect the other bit changing the reading, programming and erase characteristics of the cell in subsequent cycles. Eventually, the buildup of residual or leakage charge changes the effective VT of the CB and the NB.
One significant problem with dual bit operation is a result of a shift in a blank read current of the complimentary bit when the normal bit is programmed and a shift in the blank read current in the normal bit when the complimentary bit is programmed. This shift in VT with the other side programmed is called xe2x80x9cCBDxe2x80x9d or complimentary bit disturb. The CB and NB regions are near the drain/source junctions of the cell and are modified during programming and erase operations. Another problem is caused by charge loss after cycling of the cell. Therefore, a major challenge for dual bit operation manifests from the combination of the charge loss and complimentary bit disturb under the two conditions: (1) CBD at BOL (beginning of life) and (2) charge loss post cycling at EOL (end of life or post bake). Test data indicates that the CBD is higher near the BOL and the VT distributions overlay the program VT after cycling and bake (EOL). The overlap of the two distributions prevents normal read sensing schemes from working correctly for dual bit operations. In other words, it cannot be determined whether the data in a CB or NB is a one or a zero because as the VT distributions approach each other.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
A system and methodology is provided for proper reading of multi-bit memory cells in a memory device (e.g., flash memory) over the life of the device (e.g. 100 K-300 K program and erase cycles). The present invention utilizes a first reference cell and a second reference cell to determine an average dynamic reference value. The average dynamic reference value is determined by reading a programmed bit of the first reference cell and reading an unprogrammed or erased bit of a second reference cell to determine an average dynamic reference value. The average dynamic reference value can be utilized to determine whether data cells are in a programmed state (e.g., logic 1) or in an unprogrammed state (e.g., logic 0). The read currents from the first reference cell and the second reference cell are averaged to determine an average dynamic reference value. The average dynamic reference value can be converted to a voltage threshold (VT) that can be compared with a VT of a data bit to differentiate a programmed bit from an unprogrammed bit.
Program and erase cycles are performed on the reference cells along with data cells of the memory device and are left blank until the xe2x80x9cpagexe2x80x9d or xe2x80x9cwordxe2x80x9d is programmed. This means that the references are the same xe2x80x9cagexe2x80x9d because they have endured a same number of cycles as the data cells to which they are being compared. Therefore, the reference cells will provide dynamic reference values that track charge loss and CBD of the associated data dells. The dynamic reference value tracks change in voltage threshold and the effects that complimentary bit disturb have on one or more data cells that occur during normal cycling of the memory device.
In one particular aspect of the invention, one bit of a first reference cell and one bit of a second reference cell is programmed prior to normal operation. A programmed bit of the first reference cell is read to track charge loss of the data cells and an unprogrammed bit is read from the second reference cell to track CBD caused by the programmed bit of the second reference cell.
In accordance with an aspect of the invention, a first reference cell and a second reference cell are associated with a word in a memory array. The first reference cell and second reference cell can be employed to determine if bits in a word are programmed (e.g., logic 1) or unprogrammed or erased (e.g., logic 0). Alternatively, a first reference cell and a second reference cell can be associated with bits in a wordlinexe2x80x94a wordline can include a plurality of words. Additionally, a first reference cell and a second reference cell can be associated with a sector or an entire memory device.
In accordance with another aspect of the invention, multi-bit flash memory cells and associated reference arrays are cycled (e.g., program and erase cycles) with multi-bit flash memory cells in the sector so that all the cells in the sectors and associated reference arrays are the same xe2x80x9cage.xe2x80x9d The associated reference arrays include a first dynamic array and a second dynamic array. A comparison circuit compares the data read from a cell to an average value derived from the first dynamic array and the second dynamic array to verify bits in the sector. The multi-bit flash memory array that allows multi-bit operation of the flash memory device by allowing the use of dual dynamic references that are cycled with the multi-bit memory cells in the flash memory.
The following description and the annexed drawings set forth certain illustrative aspects of the invention. These aspects are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.